The active clamp switching topology for DC/DC converters is well known in the field of electronic power conversion, and its advantages and operation are described by Leu, et al. Further explanation of its operation and circuit variations are described by Vinciarelli (RE-36,098), Boylan (U.S. Pat. No. 5,327,333), Jacobs (U.S. Pat. No. 6,288,920), Fraidlin (U.S. Pat. No. 6,377,476), and Boylan (U.S. Pat. No. 6,445,598). Numerous switching circuit topologies are known that provide practical means of dc-dc conversion, for example, variations of the full and half bridge topologies, the flyback topology, the SEPIC topology, and others. But an outstanding characteristic of the active clamp topology is its ability to provide a minimum sustained voltage stress on the output rectifying diodes when the power supply is required to operate over a range of input voltages. This characteristic may allow the use of lower voltage-rated parts for the output diodes, providing both performance improvement and lower cost.
The active clamp topology is configured with two active switches on the primary side of the power transformer that alternately conduct during substantially non-overlapping/contiguous time periods during a switching cycle. One switch, the primary switch, closes for a duty cycle D to couple the primary of the power transformer to an input power source, and then a second switch, the reset switch, coupled to a clamp capacitor and the primary of the power transformer, closes for a complementary time period 1-D to reset the flux in the power transformer to substantially its value at the beginning of a switching cycle. A characteristic of the active clamp topology in many practical applications is the ability to close the reset switch at any rated load with insignificant turn-on loss, i.e., with zero-voltage switching (ZVS). This requires a brief delay between turn-off of the primary switch and turn-on of the reset switch, and this timing is generally not critical because the body diode in a MOSFET transistor, which is the common but not required implementation of these active switches, automatically conducts at the required turn-on time. If a switch technology different from a MOSFET is used, a diode is assumed effectively to be in parallel with the controlled terminals of the switch to reduce the switch turn-on timing uncertainty.
However, the switching transition from the reset switch conducting to the primary switch conducting often does not result in ZVS at higher rated load currents for the active clamp power converter. This occurs because the current in the magnetizing inductance of the power transformer, which is a principal energy source to enable ZVS for this switching transition, is often insufficient to counteract the output current reflected to the primary winding of the power transformer at higher load currents. The reflected output current flows in the primary winding in a direction opposite to the direction of the magnetizing current at this time. Reducing the magnetizing inductance of the power transformer to increase the magnetizing current is usually not practical because reducing the magnetizing inductance generally increases power loss due to a resulting higher level of recirculating current. The result is only a partial reduction in the voltage across the primary switch when the reset switch is opened at higher output currents. The switch voltage rings with parasitic circuit capacitance and inductance until the primary switch is enabled to conduct. Thus, the primary switch is turned on while sustaining substantial voltage across its controlled terminals, resulting in loss of energy stored in parasitic capacitance. Turning on the primary switch without ZVS may also cause additional losses elsewhere in the circuit.
Thus, while the active clamp topology has benefits such as a low voltage rating for the rectifying diodes and ZVS for the reset switch, it suffers from inability to provide ZVS during the transition from the reset switch conducting to the primary switch conducting at higher load currents. Accordingly, what is needed in the art is a way to preserve the benefits of the active clamp circuit topology while providing a way to achieve ZVS or substantially reduced switch voltage during the reset-to-primary switching transition at higher load currents, thereby providing reduced switching losses for the converter.